Eastoe, J; Noah, G M; Dutta, D; Rossi, A; Fletcher, J D; Gomez-Saiz, A (2024) Method for efficient large-scale cryogenic characterization of CMOS technologies. IEEE Transactions on Instrumentation and Measurement, 74. 2000210

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Abstract

Semiconductor integrated circuits operated at cryogenic temperature will play an essential role in quantum computing architectures. These can offer equivalent or superior performance to their room-temperature counterparts [1] while enabling a scaling up of the total number of qubits under control. Silicon integrated circuits can be operated at a temperature stage of a cryogenic system where cooling power is sufficient (∼ 3.5+ K) to allow for analog signal chain components (e.g. amplifiers and mixers), local signal synthesis, signal digitization, and control logic. A critical stage in cryo-electronics development is the characterization of individual transistor devices in a particular technology node at cryogenic temperatures. This data enables the creation of a process design kit (PDK) to model devices and simulate integrated circuits operating well below the minimum standard temperature ranges covered by foundry-released models (e.g. -55 °C). Here, an efficient approach to the characterization of large numbers of components at cryogenic temperature is reported. We developed a system to perform 4-wire Kelvin DC measurements of individual transistors at 4.2 K using integrated on-die multiplexers, enabling bulk characterization of thousands of devices with no physical change to the measurement setup.

Item Type:	Article
Keywords:	Cryo-CMOS, cryogenic electronics, I–V curves, MOSFET, quantum computing, semiconductor device modeling, silicon-on-insulator (SOI)
Subjects:	Electromagnetics > Electrical Measurement
Divisions:	Quantum Technologies
Identification number/DOI:	10.1109/TIM.2024.3497143
Last Modified:	22 Aug 2025 13:23
URI:	https://eprintspublications.npl.co.uk/id/eprint/10217