< back to main site


Test procedure for process validation with surface insulation resistance.

Brewin, A; Zou, L; Hunt, C (2002) Test procedure for process validation with surface insulation resistance. NPL Report. MATC(A)121

[img] Text

Download (607kB)


Surface Insulation Resistance (SIR) testing uses a test circuit with a comb pattern design to which a bias voltage can be applied, and leakage current measured. The effects of voltage and combs patterns pitch are critical to the behaviour of process residues and their effect on SIR. Calculations assuming homogeneous sheet resistance and electric field are not valid and cannot be used to predict the performance for electronic devices with differing geometries.
This work shows that electronics manufacturers measuring the effect of process residues must consider the geometries of the SIR test sites, which need to be representative to produce meaningful SIR data.
Furthermore the reality of the production process for a typical printed circuit assembly (PCA) leaves residues from numerous chemical processes, not just the soldering flux. In order for the potential impact on reliability for all of these to be assessed a test vehicle should be used and prepared via the production line of interest.
This report outlines a procedure for the validation of an electronics manufacturing process using SIR. It offers guidance for the design of test vehicles appropriate for production processing. SIR data collected using this procedure is more representative than that based on flux qualification.

Item Type: Report/Guide (NPL Report)
NPL Report No.: MATC(A)121
Subjects: Advanced Materials
Advanced Materials > Electronics Interconnection
Last Modified: 02 Feb 2018 13:17
URI: http://eprintspublications.npl.co.uk/id/eprint/2479

Actions (login required)

View Item View Item